// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:07 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_gen_clk_or2.v
//
//  Generic clock OR for synthesis use
//
//  Original Author: Ross Segelken
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_gen_clk_or2.v $ 
//    $DateTime: 2015/04/09 20:58:28 $
//    $Revision: #1 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_ani_techcell_lib.v"

module dwc_e12mp_phy_x4_ns_pcs_raw_gen_clk_or2 (
output wire out,
input  wire clk1,
input  wire clk2
);

// %%SYNTH:
//   set_size_only -all_instances [get_cells $inst/hand_buf]
//
`ifdef ANI_SYNTH_MODE
   dwc_e12mp_phy_x4_ns_ani_clk_or2 hand_buf(.Y(out), .A(clk1), .B(clk2));
`else
   assign  out = clk1 | clk2;
`endif

endmodule
